Since the design rule for fabricating semiconductors has been greatly reduced in recent years, various technologies in semiconductor design and manufacturing have been highly developed. On the other hand, the market always has strong demand to manufacture cheaper, smaller, and lighter electronic products with better performance and more functions. The number of electronic device on a single chip is rapidly growing to meet this demand but the ability of two dimensional layouts in circuit design and fabrication to accommodate these demands has reached its limits.
Currently, three-dimensional integrated circuits (3D-ICs) provide breakthroughs to this bottleneck. A 3D-IC is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single integrated circuit. This is also referred to three-dimensional stacking, corresponding to a wafer level packaging technique in which specific components are fabricated on separate wafer platforms and then integrated onto a single wafer-scale or chip-scale package with through-silicon vias (TSVs) to provide electrical interconnections between the components inside the 3-D stack. TSVs provide a variety of advantages such as higher integration, better system performance, less power consumption, and lower parasitic losses. Consequently, many chip designers and manufacturers have shifted to this novel technique.
Electrodeposition is a frequently-used method to deposit different conductive metals into vias for forming electrical connections. Nevertheless, voids, insufficient filling, and non-uniform deposit are frequently found during via filling through electroplating, and such defects generate adverse effects to the devices.
In general, there are many parameters dictating the quality of vias including plating bath, via geometry, and additives used. In addition, the concentration and type of additives, via shape, aspect ratio (depth/width), current loading, and deposition time are frequently studied so as to optimize the electrodeposition process.
A traditional approach for investigating how the abovementioned parameters affect the process is through experiments. Vias in wafers are firstly electroplated under different parametric values and the processed wafers are cut for examining the cross section of the vias by an optical or a scanning electron microscope. In general, the time for depositing metal into vias takes about one hour. Then, the time for preparing the cross section of the vias, following with examination by a microscope is around 2-3 hours. Although investigating through experiments is able to provide solid results but this process for fabricating and characterizing the vias is extremely time consuming. For instance, if there are six process parameters to be studied and adjusted in a process, it may induce more than several hundreds of experiments because of the possible permutations of parameters, making such approach practically unfeasible.
For solving the abovementioned problems, computer simulation is deployed to simulate the electroplating process for determining the suitable process window of process parameters. For example, U.S. Pat. No. 7,279,084 discloses an electroplating method, which uses a computer to generate a model for calculating the current ratio between an inner anode and outer anode.
Nevertheless, accuracy of computer simulation is always a major concern. More consideration factors and more detailed models can be used to enhance accuracy of a computer simulation. However, the time and computing resources needed for running such computer simulation will increase enormously at the same time. Furthermore, in some cases, a wrong assumption or value used in the computer simulation may generate significant errors leading to useless simulation results for use in manufacturing.
Therefore, there is an unmet need to provide an accurate, fast, and cost effective method for evaluating performance of electroplating formulation of electrolyte solution used for via filling.